Despite significant challenges to device scaling, Moore's Law has continued to be a driver for the semiconductor industry. In order to continue conventional CMOS device scaling to its extreme theoretical limit and to keep Moore's Law on track, technologists are using strain engineering to further enhance and extend device performance. As opposed to junction engineering, gate oxide scaling or poly CD reduction, strain engineering alone is able to deliver enough performance boost to enable Moore's Law beyond the 90 nm node.
The nearly 4.2% lattice mismatch between single crystal Ge and Si lattice structure has been the foundation of strain engineering in the silicon industry. The electronic conduction and valence band structure of SiGe was well established following the early preparation of homogenous SiGe alloys nearly four decades ago. The advent of pseudomorphic deposition of Si on GexSi1−x extended this understanding to strained lattice structure and enabled examination of electrical characteristics of strained Si.
The work predicted strained Si to have higher carrier mobility compared to the relaxed Si lattice structure. The enhanced mobility in strained Si is partly due to reduced inter valley phonon scattering and lower effective mass. The induction of localized strain via deposition of dielectric films is an alternative form of inducing localized stress in the channel of sub-90 nm devices. Such films as salicide, oxide and nitride spacers can affect device performance by inducing strain in addition to other effects.
Despite its compressive nature and degradation in NMOS mobility, High Density Plasma Chemical Vapor Deposition (HDP-CVD) is currently the most commonly used gapfill technology for shallow trench isolation (STI) applications due to ease of polishing and superior wet etch rate results. Moving forward however, the issue of stress and the degradation of NMOS mobility caused by films deposited via HDP technology could be a significant process disadvantage as geometries shrink. For example, although STI depth has remained nearly constant in the past few technology nodes, the pitch in a 65 nm node could be as aggressive as <200 nm. Combined with an estimated poly pitch of less than 200 nm, trench processing can induce significant stress in the channel of the minimum design rule structures.
Considerable reduction of NMOS Idsat is observed as the device width decreases, for a given device length. This indicates that the effect of HDP compressive stress is more profound on the NMOS device performance, while PMOS performance remained unaffected by decreasing width. Thus there remains a need for materials and processes to fill gaps in STI applications that enhance, rather than degrade, the performance of NMOS devices. There also remains a need for materials and processes that enhance NMOS while not degrading the performance of PMOS devices.